The present application relates to semiconductor device fabrication, and more specifically to the fabrication of vertical gated diodes using a gate-last process flow.
Vertical field effect transistors (FETs) are attractive candidates for 5 nm node and beyond technologies due to better density scaling and better control of electrostatics. Gated diodes are often used in conjunction with FETs in complementary metal oxide semiconductor (CMOS) integrated circuits for important analog circuit functions including temperature sensing and bandgap reference voltage applications. Vertical FETs are commonly formed by a gate-last process flow. A method for fabrication of gated diodes that is compatible with the gate-last process flow is thus desirable for integration of vertical FETs and gated diodes.